Hi there! I’m Lai-YT

I’ve been working on GPU architecture and compiler optimization, with a particular focus on how warp-level memory access patterns interact with the GPU memory hierarchy, especially the L1 cache. This work eventually became my master thesis, where I explored how a compiler can select memory layouts that better match different access patterns. Along the way, I became quite familiar with conventional SIMT execution and GPU performance analysis.

Now, I’m shifting my focus toward large language models (LLMs). Modern GPUs increasingly rely on specialized hardware¹ and asynchronous execution mechanisms that play an important role in LLM computation. I’m interested in understanding these newer execution models and how they can be used to optimize LLM workloads. I’m also interested in the related hardware-software co-design.

Interest

• Coffee
  • Like acidity more than bitterness.
  • Coffee Review (Chinese)
• Books
  • Book Recommendations (Chinese)
• Table Tennis
  • Blade: Nittaku Acoustic, F: XIOM Vega Pro (Max), B: Nittaku Fastarc C-1

Other

• Master Thesis: Improving Intra-Warp Cache Utilization on GPUs through Compiler-Guided Exploitation of Texture Hardware
  • Thesis (158 pages)²
  • Slides
• Resume

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1. For example, tensor cores for high-throughput matrix operations and the Tensor Memory Accelerator (TMA) for asynchronous data movement. ↩

2. The thesis is also available online at NYCU Institutional Repository. The repository version is a double-sided printed version. ↩